The present invention relates to charge-coupled devices and in particular to a storage cell for a serial-parallel-serial, charge-coupled device exhibiting a bidirectionally tilted channel potential.
A charge-coupled device is an integrated circuit including a row of closely spaced charge storage cells. Each storage cell includes an electrode formed on an insulation layer covering a semiconductor substrate, the substrate of each cell having a channel region for storing packets of charge carriers. When electrodes of neighboring storage cells are biased by clock signals of differing phase, an electric field develops between channel regions within or on the surface of the substrate beneath the electrodes of the storage cells, and this electric field drives charge carriers in the channel region of one cell into the channel region of its neighboring cell. By applying appropriately phased clock signals to electrodes of neighboring cells of a charge-coupled device, charge packets are shifted laterally from cell-to-cell.
A "serial-parallel-serial", charge-coupled device (SPSCCD) employs a planar, two-dimensional array of storage cells, rather than just a single row of storage cells. After a sequence of charge packets is serially shifted into a first row of cells, the charge packets stored in cells of the first row are shifted in parallel from row-to-row until they reach the last row of the array. The charge packets are then serially shifted out of the last row.
A serial-parallel-serial, charge-coupled device may be used in a high frequency digital oscilloscope for storing a sequence of charge packets acquired by periodically sampling an analog input signal. The oscilloscope rapidly shifts charge packets into the SPSCCD as it samples the analog signals at a high sampling frequency, the amount of charge in each packet being proportional to a sampled voltage of the input signal. When every row of the SPSCCD stores a sequence of charge packets, the charge packets are shifted out of the SPSCCD at a slower rate and converted to a corresponding voltage input to an A/D converter. In response, the A/D converter generates a sequence of digital data representing the analog input signal, and the data sequence controls a waveform display. Since the SPSCCD acts as a buffer slowing application of voltage input to the A/D converter, the A/D converter may operate at a frequency lower than the sampling frequency.
During initial stages of high speed serial charge packet transfer between adjacent storage cells of the first row of the SPSCCD, or parallel charge packet transfer between cells of the first and second row, clock-induced potential gradients between the channel regions of adjacent storage cells provide strong electric fields driving carriers quickly from one cell to another. A high carrier concentration gradient between channel regions of adjacent cells also encourages carrier flow by diffusion. However, as charge carriers begin to accumulate in a receiving cell, both the carrier concentration gradient and the clock-induced potential gradient between the channel regions of adjacent storage cells decrease, thereby slowing diffusion and drift of remaining carriers into the channel region of the receiving cell. As the frequency of clock signals applied to the electrodes of storage cells increases, the time available for charge carriers to move from one cell to its neighboring cell decreases. At high clock frequencies, a substantial portion of carriers of a charge packet remains behind at the end of a clock phase.
The "charge transfer efficiency" of a charge-coupled device is the ratio of charge transferred to a storage cell from its neighboring cell during a clock phase to the initial charge in the neighboring cell at the beginning of the clock phase. As the frequency of operation of a charge-coupled device increases, charge transfer efficiency decreases. A high charge transfer efficiency is desirable, particularly in large SPSCCDs having many storage cells, to prevent substantial degradation of charges passing through the device. Charge transfer efficiency of an SPSCCD can limit its frequency of operation.